CSP Hardware Bus Contention Demo

The following applet uses the Ptolemy II CSP domain to model resource contention. The model shows the use of timed CSP to deterministically handle nondeterministic events.

Applet Description:

The applet consists of a controller, three processors and a memory block. At randomly selected points in time, each processor can request permission from the controller to access the memory. The processors each have priorities associated with them, and in cases where there is a simultaneous memory access request, the controller grants permission to the processor with the highest priority.

All communication between actors in a CSP model of computation occurs via rendezvous. Rendezvous is an atomic form of communication. This model uses a timed extension to CSP, so each rendezvous logically occurs at a specific point in time.

Because of the atomic nature of rendezvous, when the controller receives a request for access, it cannot know whether there is another, higher priority request pending at the same time. To overcome this difficulty, an alarm is employed. The alarm is started by the controller immediately following the first request for memory access. It is awakened when time is ready to advance (the model blocks on delays). This indicates to the controller that no more memory requests will occur at the given point in time. Hence, the alarm uses centralized time to make deterministic an inherently non-deterministic activity.

In the applet, each of the initially blue processors (the circular nodes) can be in one of three states. The color yellow indicates that a processor is in state 1 and is waiting for the controller to give it permission to access memory. The color green indicates that a processor has been granted permission to access memory. The color red indicates that the processor has been denied memory access.

This applet consists of four types of actors:

The applet code is implemented via: