Controllers
This model shows two (independent) control loops whose controllers
share the same CPU. The control loops are chosen such that it is
unstable if the control signals are constantly delayed. By choosing
different priority assignments and TM scheduling policies, different
stability of the two loops may appear. For example, a nonpreemptive
scheduling can stablize both control loops, but none of the preemptive
ones can.
The block diagram
for the model was constructed using the Ptolemy II schematic editor
called Vergil.